How to do binary to gray code conversion -

SAN MATEO, Calif., April 5, 2021 – OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a Die-to-Die (D2D) PHY that complements the company’s existing D2D Controller to offer complete D2D interface solutions for various packages including substrates and interposers.

An application-specific integrated circuit (ASIC) ,is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use.

There are different phases in Asic design cycle , We will go through each cycle and understand from basics.

Max transition (clock or data) is the maximum slew that is allowed at the cell input pin.
This comes either from the library, or it can come from a manually constrained file from the designer.
Similarly, max capacitance check limits the allowed capacitance on the output pin of a cell.

Below are the link for a quick review of verilog language

http://www.tcnj.edu/~hernande/Eng312/TCNJ_Verilog(R)_V05.pdf

Click on main heading for detail information.

Verilog code to calculate the square root of a number ->

------------------Start of Verilog Code --------------------

`timescale 1ns/100ps

Round Robin algorithm details :
Round Robin algorithm Verilog code :

What is Round Robin algorithm ?

Binary to 7-segment LED display is very easy , it is more like the decoding logic.

Below is the rtl code in Verilog for the same.

7 -Segment Display ->

>Interview Questions on Error Correction and Detection  ->

1. What is the difference between ECC and CRC ?

2. What are the different technique to detect Error ?

Circuit diagram for posedge detector and negedge detector :

Below link is the UPF example, I have tried my best to put all things in one page to get better understanding.

You might have to adjust your display setting to view it properly. 

Verilog code to detect Pattern Detecting pattern is come in Digital design and it is most commonly question during the interview.

Here is one example of detecting " 100110 " pattern using a FSM.

Transaction Layer Packets, or TLPs which contain a header, data payload, and optionally an end-to-end CRC, ECRC. The ECRC, if used, is generated by the user logic at the transmitter and checked by the user logic at the receiver.

UART (Universal Asynchronous Receiver/Transmitter)/USIM are used for communication between two devices through serial line. The primary function of UART/USIM is parallel to serial conversion when transmitting and serial-to-parallel conversion when receiving.

Transmitter   ->  This is the device that transmits data to the bus
Receiver         ->  This is the device that receives data from the bus
Multi-master  -> I2C can have more than one master and each can send commands