Here is the verilog code for counting number of 1's and number of 0's in parallel data. since data is continuously changing on every clock cycle,  counting has to be done using parallel hardware. Below is the code with testbench and simulation result :-

Does anyone know what will be the hardware synthesis tool will make ?

Is it going to be encoder , or  multiple adders or full of mux ??

---------------------------- Verilog Code ------------------

module count1n0 (
input clk,
input rstn,
input [9:0] data,
output reg [3:0] num_of_one,
output reg [3:0] num_of_zero
);

 

 always @(*) begin
      num_of_one  = 4'b0;
      num_of_zero = 4'b0;

    if(!data[0])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one + 1 ;

    if(!data[1])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[2])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[3])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[4])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[5])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[6])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[7])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[8])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

    if(!data[9])
      num_of_zero = num_of_zero + 1;
    else
      num_of_one = num_of_one +1 ;

  end

endmodule
------------------------------------------------------

------------------- Verilog Testbench ----------------

module tb;

reg clk;
reg rstn;
reg [9:0] count;
wire [3:0] one;
wire [3:0] zero;

initial begin
clk =0;
rstn =0;
count =0;
end

initial begin
#100;
rstn = 1 ;
#1000;
$finish;
end

initial $monitor("data = %b, num of zero = %d, num_of_one = %d ", count , zero, one);

always @(negedge clk) begin
count = count + 1297;
end

always #5 clk = ~clk ;

count1n0 dut (
.clk(clk),
.rstn(rstn),
.data(count),
.num_of_one(one),
.num_of_zero(zero)
);

initial begin
 $recordfile("test.trn");
 $recordvars();
end

endmodule