It is necessary to manage most of the verification tasks, such as generating stimulus and collecting coverage data, at the transaction level, which is the natural way of verification engineers tend to think of the activity of a system.

Many times we might use the Base Class or Base Class library provided by third party sources. By default, These Class Members are Public in nature.

While learning System Verilog you always thought like How do you pass information between two threads/processes? 

Polymorphism is the ability  to have the same code act differently based on the type of the Object that its being working with. This is a key topic of any Object Oriented Programming language. SystemVerilog enables 

STATIC Properties: As we know that in SystemVerilog Class Properties do not get created until the Object gets constructed. But there is an exception to that. When we add a “static”

Before we start understanding the “logic” data type for system Verilog, Let’s refresh verilog data types “reg” and “wire”. 

Concept and usage of “this” is simple but important in test bench development using system verilog. I would like to share some insights on this concept.

Shallow Copy:

As we know that Classes contains Properties and Methods. A Class may also contain other Class Instantiation as a part of it. All these variables inside a Class got initialized once the Class is constructed.

To start a UVM Testbench, the run_test() method has to be called from the static part of the Testbench i.e called from an initial block in the top module of the Testbench.

Today I’m going to share something which is so common to almost every concept of UVM. In other way, we can say that this concept is the backbone of the UVM Verification Methodology. This is related to the process which deals from the starting of the simulation till end of the simulation.

Functional Coverage is very important in Test Bench Development. It always gives us a confidence on covered items listed on verification plan. 

Coverage is used as a metric for evaluating the progress of a verification project. Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of constrained random testbenches. 

1. What is the difference between code coverage and functional coverage?

There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification process.

Sometimes user will face a situation where you need some of the components from environment to demote error message means user want to disable error from a specific component.