Verilog HDL operators are same as in C language.

{}   - concatenation 

usage -

reg ab;
reg [1:0] cd ;
reg  [2:0] z ;

always @(*) begin
   z = {cd, ab} ;
end

{3{A} } //  this is equivalent to { A, A, A}
{2 {X, Y}, Z} is equivalent to  {X, Y, X, Y , Z}

+, - , * , /   - arithmetic 

usage -
used in conventional way ..  A = B + C ;

if B and C is 4 -bit , then A should be 5-bit (sum + carry)


%   --  modulus

example - 10 %3  will give remainder 1

> >= < <=    ---  relational

a a>b      a greater than b
a<=b    a less than or equal to b

a>=b    a greater than or equal to b

!    --  logical negation

!a  -  invert of a

&&  -- logical and
This is not a bit wise logical AND , bit wise is &

||    --  logical or
This is not a bit wise OR , bit wise is |

==     ---    logical equality
example
a == b a equal to b, result may be unknown


!=      ---   logical inequality
example
a != b a not equal to b, result may be unknown

=== case equality
example
a === b a equal to b, including x and z

!== case inequality
example
a !== b a not equal to b, including x and z

~ bit-wise negation

& bit-wise and

| bit-wise inclusive or

^ bit-wise exclusive or

^~ or ~^ bit-wise equivalence

<<   left shift

>>   right shift


?: conditional


Verilog having syntax restriction for using space , please see below for details.

X & &Y    and X && Y  is  not same ,
X | |Y  and  X |  |Y  is not same.

It is always better to use parenthesis for nested kind of operations.

I think those are the operators which we used normally in RTL coding , there are other operators like string manipulation, but those we don't use in RTL coding.

Please let me know If I missed something here

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