Any type of Testbench typically requires following two sections to verify a targeted DUT:Stimulus Generation

Analysis of the Design Response

In normal scenarios the synchronization of hardware events, like clocks, resets, error signals, interrupts etc., primarily takes place inside the UVM Driver & Monitors for an UVM Testbench.

Many times we might use the Base Classes or Base Class library provided by other teams or third party sources. We’ve seen how to access the Class Properties and Methods i.e. “Class Members” in SystemVerilog using the Class Handles. By default, These Class Members are Public in nature. It means these Class

Hii!  Welcome to SystemVerilog OOP – Part 2. I hope you’ve already gone through SystemVerilog OOP – Part 1, where we touched base with different key concepts in OOP like Encapsulation, Inheritance, Data Hiding, Parametrizaton & Polymorphism.

Hello All!, I wanted to write for SystemVerilog category since a long time but UVM Testbench Architecture category contains so many interesting topics to write about that whenever I wanted I fall-in for the Testbench category.

Before explaining the Sequence Arbitration lets have a very quick Sequences recap – UVM Sequences are used to generate input stimulus for the Design Under Test i.e. DUT. Sequences are executed on a particular Sequencer which passes the generated Transactions to the connected Driver.

Interrupt handling is a well known feature of any SoC which usually comprises of CPU, Bus Fabric, several Controllers, Sub-Systems & many IP blocks as part of it. In some way or other Interrupts are used to act as the sideband signals of the Design/IP Blocks & most of time its not the part of main bus or control bus.

How to connect the DUT to the UVM Testbench..??

In our traditional directed Testbench environments, all the components are “static” in nature & information (data/control) is also exchanged in the form

We discussed about “Sequences” in my previous post titled “UVM Sequences and Transactions Application“.  Here, we’ll talk about “Hierarchical Sequences“. Following are the questions most likely pops-up into our mind the moment we think about Hierarchical Sequences.

Hi Friends, in my previous Functional Coverage blog, I’ve shared high level idea & understanding about Coverage & types of Coverage i.e. Code Coverage & Functional Coverage with an example of Coverage data model i.e. cover groups.

Hi! As we already know that UVM Driver plays a very significant role in interface protocol implementation since it deals with class based transaction or sequence items on one side and on the other side works at clock based signal/pin level activities.

Electronic gadgets are an integral part of our day-to-day life. Lifeline of these gadgets/products are semiconductor IC/SoC/ASIC/FPGA which are mounted on the PCB (Printed Circuit Boards) & connected with each other to make the gadget operational.