In electronics, a delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator, replaced by a delay line.
A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform), usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits (such as DRAM devices). DLLs can also be used for clock recovery (CDR). From the outside, a DLL can be seen as a negative-delay gate placed in the clock path of a digital circuit. 1)
A PLL controls a voltage-controlled oscillator in order to bring its frequency (or some derivative of it) into phase (and frequency) lock with a reference signal.
PLLs have many applications, from creating a "clean" replica of a noisy reference signal (with amplitude and phase variations removed), to creating new frequencies through multiplication and division, to demodulating phase- and frequency-modulated communications signals. The input-to-output transfer characteristics of a PLL can be controlled through the design of its feedback network. A DLL controls a voltage-controlled delay line, which typically has many taps, in order to bring one of those taps into phase alignment with a reference signal. The input to the delay line is usually also the reference signal, so the various taps provide additional signals that are interpolated and/or extrapolated from the period of the reference signal.
While the mentioned above (i.e. clean version of signal -> PLL) a key aspect of where PLLs/DLLs differ is that PLL's filter and effectively block jitter in the source from affecting the VCO output, whereas DLL's propagate jitter. At first this may appear to be a negative aspect of DLL's but it can be used to great effect. In some cases you need to pull the main sampling point from the signal that is arriving and ignore the jitter in the signal, you would use a PLL. In other cases, say when a signal and clock signal are subjected to the same jitter inducing effects either at the source or in the communications channel. You can use a DLL and multiple sampling delay times to reduce/eliminate the relative jitter between the two signals (because they have the very similar jitter) and use the delayed clock to align to an ultimate sampling point
3)
Other difference between a DLL and a PLL is that a DLL uses a variable phase (=delay) block where a PLL uses a variable frequency block.
4)
A DLL compares the phase of its last output with the input clock to generate an error signal which is then integrated and fed back as the control to all of the delay elements. The integration allows the error to go to zero while keeping the control signal, and thus the delays, where they need to be for phase lock. Since the control signal directly impacts the phase this is all that is required.
A PLL compares the phase of its oscillator with the incoming signal to generate an error signal which is then integrated to create a control signal for the voltage-controlled oscillator. The control signal impacts the frequency of the oscillator, and phase is the integral of frequency, so a second integration is unavoidably performed by the oscillator itself.
5)
DLL is a loop of 1st order and type 1 .
PLL of 2nd order and type 2
Without the integration of the error signal, the DLL would be 0th order and type 0 and the PLL 1st order and type 1.
6)
The number of elements in the delay chain must be even, or else the duty cycle of the clock at the intermediate nodes of the chain might become irregular.
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