module CPU_Model
(
pclk,
pready,
//address,
//data,
pwrite,
psel,
penable,
pwdata,
pwaddress
);

//Tin hieu xung
input pclk;
input pready;
//Tin hieu dieu khien
output psel, penable, pwrite;
//Tin hieu du lieu
output [7:0]pwaddress;
output [7:0]pdata;

task MOVT; 
input [7:0]address;
input [7:0]data;
// Xung thu 1
@(posedge pclk)
begin
	#1;
	pwrite=1;
	psel=1;
	paddress = address;
	pdata = data;
	penable = 0; // missing 
end

//Xung thu 2
@(posedge pclk)
begin
	#1;
	penable = 1;
end

//Xung thu 3 tro di
@(posedge pclk) // No always
begin
	//if(pready) // no wait state
	//begin
	//    #1;
	//	psel =0;
	//	penable =0;
	//end
	//else
	//begin
	    //@(posedge pclk)
		while (!pready)
           @(posedge clk);    		
	    /// ???????????????
		#1; 
		psel = 0;
		penable = 0;
	//end
end

endtask 

endmodule