Functional Coverage is very important in Test Bench Development. It always gives us a confidence on covered items listed on verification plan. 

Usually the goal of verification engineer is to ensure that the design behaves correctly in its real environment according to specifications.

Defining coverage model is very important for any test bench development to get enough confidence on design verification.

Here I would like to share some of the important feature of SystemVerilog Functional Coverage which helps user during verification activity.

Coverage Options available in System Verilog through which you can specify additional information in the cover group using provided options

1. Cover Group Comment – ‘option.comment’

You can add a comment in to coverage report to make them easier while analysing:

covergroup CoverComment ;

  option.comment = "Register Definition section 1.1";

  coverpoint reg;

endgroup

In example, you could see the usage of ‘option.comment’ feature. This way you can make the coverage group easier for the analysis.

2. Per Instance Coverage – ‘option.per_instance’

In your test bench, you might have instantiated coverage group multiple times. By default System Verilog collects all the coverage data from all the instances. You might have more than one generator and they might generate different streams of transaction. In this case you may want to see separate reports. Using this option you can keep track of coverage for each instance.

covergroup CoverPerInstance ;

  coverpoint tr.byte_cnt;

  option.per_instance = 1;

endgroup

3. Threshold using – ‘option.at_least’ 

This feature is useful when you don’t have sufficient visibility in to the design to gather robust coverage. There might be cases where you just have an information of number of cycles that are needed for the transfers to cover required errors to get generated/simulated for defined cover point. Here you could set the option.at_least. For example, if we know that we need 10 cycles to cover this particular cover point, you could define option.at_leaset = 10.

4. Control on Empty bins – option.cross_num_print_missing = 1000

System Verilog coverage report by default shows only the bins with samples. But usually as a verification engineer, our job is to verify all cover points that are listed in the verification plan.

covergroup CoverCrossNumPrintMissing ;

ByteCnt : coverpoint tr.byte_cnt;

Length : coverpoint tr.length;

   option.cross_num_print_missing = 1000;

endgroup

5. Coverage Goal – option.goal

In system verilog, coverage goal for a cover group or point is the level at which the group or point is considered fully covered.

covergroup CoverGoal ;

    coverpoint tr.length;

    option.goal = 80;

endgroup

These are the few important coverage option features which are very useful in defining/coding System Verilog Functional Coverage.